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general description the hi-3717 from holt integrated circuits is a cmos device designed for interfacing an arinc 717 compatible bus to a serial peripheral interface (spi) enabled micro-controller . the part includes a selectable harvard bi-phase (hbp) or b i - p o l a r r e t u r n - t o - z e r o ( b p r z ) r e c e i v e c h a n n e l a n d transmit channels with hbp and bprz encoders and line drivers. the receive channel has integrated analog line receivers and the transmit channels have integrated line drivers for the corresponding encoding method (hbp and bprz). the part operates from a single +3.3v supply using only four external capacitors. each transmit and receive channel has a 32-word by 12-bit fifo for data buf fering. the hi-3717 is available in very small 44-pin 7mm x 7mm chip-scale (qfn) and 44-pin quad flat pack (pqfp) plastic packages. pin configura tions (t op v iew) single-rail arinc 717 protocol ic with spi interface november 201 1 hi-3717 ( d s 3 7 1 7 r e v . b ) 1 1 / 1 1 44 - pin plastic 7mm x 7mm chip-scale package (qfn) 44 - 43 - vdd 42 - c1- 41 - c1+ 40 - v+ 39 - 38 - gnd 37 - c2+ 36 - c2- 35 - v - 34 - txha noconv - 1 rinb-40 - 2 rinb - 3 rina - 4 rina-40 - 5 gnd - 6 tfifo - 7 tempty - 8 insync - 9 sync0 - 10 sync1 - 1 1 33 - 32 - txoutha 31 - txouthb 30 - outhb 29 - txhb 28 - txba 27 - outba 26 - txoutba 25 - txoutbb 24 - outbb 23 - txbb outha ma tch - 12 rfifo - 13 rovf - 14 mr - 15 rsel - 16 gnd - 17 si - 18 sck - 19 so - 20 cs - 21 aclk - 22 hi-3717pci HI-3717PCT hi-3717pcm h o l t i n t e g r a t e d c i r c u i t s w w w. h o l t i c . c o m 44 - pin plastic quad flat pack (pqfp) hi-3717pqi hi-3717pqt hi-3717pqm 44 - 43 - vdd 42 - c1- 41 - c1+ 40 - v+ 39 - 38 - gnd 37 - c2+ 36 - c2- 35 - v - 34 - txha noconv - 1 rinb-40 - 2 rinb - 3 rina - 4 rina-40 - 5 gnd - 6 tfifo - 7 tempty - 8 insync - 9 sync0 - 10 sync1 - 1 1 33 - 32 - txoutha 31 - txouthb 30 - outhb 29 - txhb 28 - txba 27 - outba 26 - txoutba 25 - txoutbb 24 - outbb 23 - txbb outha ma tch - 12 rfifo - 13 rovf - 14 mr - 15 rsel - 16 gnd - 17 si - 18 sck - 19 so - 20 cs - 21 aclk - 22 fea tures compliant with arinc 717 and arinc 573 standards operates from a single +3.3v supply with on-chip converters to provide proper voltages for both harvard bi-phase (hpb) and bi-polar return-to-zero (bprz) outputs one selectable receive channel as hbp or bprz with integrated analog line receiver both hbp and bprz transmitters have integrated line drivers as well as digital outputs 32-word by 12-bit fifos for both the receive and the transmit channel programmable slew rates on transmit channels: 1.5 s, 7.5 s or 10 s digital transmitter outputs available for use with external line drivers programmable bit rates: 384, 768, 1536, 3072, 6144, 12288, 24576, 49152 and 98304 bits/sec (32, 64, 128, 256, 512, 1024, 2048, 4096 and 8192 words/sec) enhanced sync detection allows multiple false sync marks in user data while still synchronizing within 8 seconds fast spi transmitter write and receiver read modesmatch pin flags when preprogrammed word count / subframe is received frame / subframe word count indicatorindustrial and extended temperature ranges burn-in available applica tions digital flight data acquisition units (dfdau) digital flight data recorders (dfdr) quick access recorders (cassette type) expandable flight data acquisition and recording systems
40 k 37.5 control register 1 ctrl1 arinc 717 clock divider txba outba txoutba outbb rinb-40 rinb rina-40 rina 40 k spi interface t ransmit rate selection bprz encoder hbp / bprz data sampler hbp line receiver sync detect t ransmit fifo status register txfst a t w ord count utility register wrdcnt dc / dc converter receive fifo status register rxfst a t fifo status pin assignment register fspin hbp / bprz clock recovery & decoder slew rate & loopback t est control receive 32 x 12-bit fifo bprz line receiver line driver 37.5 5 5 37.5 t ransmit 32 x 12-bit fifo line driver hbp encoder control register 0 ctrl0 si so aclk rsel gnd txoutbb vdd outha txoutha outhb txhb txouthb v+ ma tch tempty sck mr noconv rovf sync1 insync v - c1+ 47uf c1- 0.47uf c2+ c2- txbb 2 . 2 u f 47uf +3.3v v - v+ txha sync0 f i g u r e 1 . cs 37.5 5 5 rfifo tfifo block diagram hi-3717 h o l t i n t e g r a t e d c i r c u i t s 2
signal function description internal pull-up / down noconv input disables on-chip dc-dc voltage converter 50k pull-down rinb-40 input alternate receiver negative input. requires external 40k ohm resistor rinb input receiver negative input. direct connection to arinc 717 bus (bprz or hbp) rina input receiver positive input. direct connection to arinc 717 bus (bprz or hbp) rina-40 input alternate receiver positive input. requires external 40k ohm resistor gnd power chip 0v supply (all gnd pins on package must be connected) tfifo output output is user programmable to indicate the t ransmit fifo full or half-full state. see fspin<5>, in t able 7, fifo status pin assignment register . tempty output output goes high when the transmit fifo is empty insync output output goes high when the receiver is synchronized to the incoming data. synchroni- zation occurs at the next valid sync mark following the detection of the proper number and order of consecutively spaced sync marks. see t able 3. sync0 output output in conjunction with sync1 output indicates when each of the four arinc 717 subframe sync words are received. only valid when the insync pin is high. sync1 output output in conjunction with sync0 output indicates when each of the four arinc 717 subframe sync words are received. only valid when the insync pin is high. ma tch output output goes high when the value of the frame w ord count register matches the value in the frame count utility register , wrdcnt . rfifo output output is user programmable to indicate the receive fifo full, half-full or empty state. see fspin<7:6> in t able 7, fifo status pin assignment register . rovf output receive fifo overflow . output goes high when an attempt is made to load a full receive fifo mr input master reset, active low 50k pull-up rsel input selects either hbp or bprz receiver . ord with rxsel bit in control register 0 50k pull-down si input spi interface serial data input 50k pull-down sck input spi clock. data is shifted into si and out of so when is low . cs 50k pull-down so output spi interface seral data output cs input chip select. data is shifted into si and out of so using sck when is low cs 50k pull-up aclk input master timing source for receiver and transmitters. 24 mhz 0.1% 50k pull-down txbb output bi-polar return-to-zero (bprz) digital low output (external line driver required) outbb output alternate bi-polar return-to-zero (bprz) line driver low output. requires external 32.5 ohm resistor txoutbb output bi-polar return-to-zero (bprz) line driver low output. direct connect to arinc 717 bus txoutba output bi-polar return-to-zero (bprz) line driver high output. direct connect to arinc 717 bus outba output alternate bi-polar return-to-zero (bprz) line driver high output. requires external 32.5 ohm resistor txba output bi-polar return-to-zero (bprz) digital high output (external line driver required) txhb output harvard bi-phase (hbp) digital low output (external line driver required) outhb output alternate harvard bi-phase (hbp) line driver low output. requires external 32.5 ohm resistor txouthb output harvard bi-phase (hbp) line driver low output. direct connect to arinc 717 bus txoutha output harvard bi-phase (hbp) line driver high output. direct connect to arinc 717 bus outha output alternate harvard bi-phase (hbp) line driver high output. requires external 32.5 ohm resistor txha output harvard bi-phase (hbp) digital high output (external line driver required) v - conver ter dc/dc converter negative voltage c2- conver ter dc/dc converter fly capacitor for v - c2+ conver ter dc/dc converter fly capacitor for v - v+ conver ter dc/dc converter positive voltage c1+ conver ter dc/dc converter fly capacitor for v+ c1- conver ter dc/dc converter fly capacitor for v+ vdd power chip +3.3v supply t a b l e 1 . pin descriptions h o l t i n t e g r a t e d c i r c u i t s 3 hi-3717
x x x x x spi instruction forma t 7 6 5 4 3 2 1 0 msb lsb x x r/w msb lsb msb lsb h i g h z high z cs so si sck (spi mode 0) figure 2. generalized single-byte t ransfer using spi protocol mode 0 serial peripheral interf ace (spi) spi basics the hi-3717 uses an spi (serial peripheral interface) for host access to internal registers and data fifos. host serial communication is enabled through the chip select (cs) pin, and is accessed via a four-wire interface consisting of serial data input (si) from the host, serial data output (so) to the host and serial clock (sck). all read / write cycles are completely self-timed. the spi protocol specifies master and slave operation; the hi-3717 operates as an spi slave. the spi protocol defines two parameters, cpol (clock polarity) and cpha (clock phase). the possible cpol-cpha combinations define four possible spi modes. without describing details of the spi modes, the hi-3717 operates in mode 0 where input data for each device (master and slave) is clocked on the rising edge of sck, and output data for each device changes on the falling edge (cpha = 0, cpol = 0). the h o s t s p i l o g i c m u s t b e s e t f o r m o d e 0 f o r p r o p e r communications with the hi-3717 . as seen in figure 2, spi mode 0 holds sck in the low state when idle. the spi protocol transfers serial data as 8-bit bytes. once cs is asserted, the next 8 rising edges on sck latch input data into the master and slave devices, starting with each byte's most-significant bit. a rising edge on cs terminates the serial transfer and re-initializes the hi-3717 spi for the next transfer . if cs goes high before a full byte is clocked by sck, the incomplete byte clocked into the device si pin is discarded. in the general case, both master and slave simultaneously send and receive serial data (full duplex), per figure 2 below . however the hi-3717 operates half duplex, maintaining high impedance on the so output, except when actually transmitting serial data. when the hi-3717 is sending data on so during read operations, activity on its si input is ignored. figure 3 and figure 4 show actual behavior for the hi-3717 so output. hi-3717 spi instructions since hi-3717 operates in half-duplex mode, the host discards the dummy byte it receives while serially transmitting the instruction op code to the hi-3717. instruction op codes are used to read, write and configure the hi-3717. each spi read or write operation begins with an 8-bit instruction. when cs goes low , the next 8 clocks at the sck pin shift an instruction op code into the decoder , starting with the first rising edge. the op code is shifted into the si pin, most significant bit (msb) first. the spi can be clocked up to10 mhz. the spi instructions are of a common format. the most significant bit (msb) specifies whether the instruction is a write 0 or read 1 transfer . for write instructions, the most significant bit of the data word must immediately follow the instruction op code and is clocked into its register on the next rising sck edge. data word length varies depending on word type written: 8-bit control & status register writes, 16-bit w ord count utility register writes and 16-bit t ransmit fifo writes. for read instructions, the most significant bit of the requested data word appears at the so pin at the next falling sck edge after the last op code bit is clocked into the decoder . as in write instructions, the data field bit-length varies with read instruction type. h o l t i n t e g r a t e d c i r c u i t s 4 hi-3717
figure 3. single-byte read from a register cs so si sck msb lsb 0 1 2 3 4 5 6 7 high z high z 0 1 2 3 4 5 6 7 msb lsb msb lsb data byte op-code byte host may continue to assert cs here to read sequential byte(s) when allowed by the instruction. each byte needs 8 sck clocks. figure 4. 2-byte spi w rite example cs so si sck spi mode 0 msb lsb 0 1 2 3 4 5 6 7 high z 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 msb lsb msb lsb data byte 0 data byte 1 op-code byte host may continue to assert cs here to write sequential byte(s) when allowed by the spi instruction. each byte needs 8 sck clocks. figure 3 and figure 4 show read and write timing as it appears for a single-byte and dual-byte register operation. the instruction op code is immediately followed by a data byte comprising the 8-bit data word read or written. for a register read or write, cs is negated after the data byte is transferred. t able 2 summarizes the hi-3717 spi instruction set. note: spi instruction op-codes not shown in t able 2 are reserved and must not be used. further , these op-codes will not provide meaningful data in response to a read instruction. t wo instruction bytes cannot be chained; cs must be negated after each instruction, and then reasserted for the following read or w rite instruction. h o l t i n t e g r a t e d c i r c u i t s 5 hi-3717
op code r/w # data bytes description 0x64 w 1 w rite control register 0 0x62 w 1 w rite control register 1 0x6a w 1 w rite receiver fifo status pin assignment register 0x72 w 2 w rite w ord count utility register 0x74 w 2 w rite t ransmit fifo word 0x2* w 1 fast w rite t ransmit fifo w ord 0xe4 r 1 read control register 0 0xe2 r 1 read control register 1 0xe6 r 1 read receive fifo status register 0xe8 r 1 read t ransmit fifo status register 0xea r 1 read receive fifo status pin assignment register 0xf2 r 2 read w ord count utility register 0xf6 r 2 read receive fifo w ord 0xfe r 4 read receive fifo w ord and w ord count 0xc* r 1 fast read receive fifo t able 3. bit name r/w default description 7 - r/w 0 not used. always reads a 0 6 - 4 br2:0 r/w 0 setting these bits sets the arinc 717 data rate for both the receive and transmit data. 000 768 bits/sec. ( 64 words/sec.) 001 1536 bits/sec. (128 words/sec.) 010 3072 bits/sec. (256 words/sec.) 01 1 6144 bits/sec. (512 words /sec.) 100 12288 bits/sec. (1024 words/sec.) 101 24576 bits/sec. (2048 words/sec.) 1 10 49152 bits/sec. (4096 words/sec.) 1 1 1 98304 bits/sec. (8192 words/sec.) 3 32wps r/w 0 setting this bit overrides the state of br2:0 and sets the data rate at 384 bits/sec. (32 words/sec.) 2-1 slew1:0 r/w 0 setting these bits controls the nominal slew rate on both the hbp & bprz transmit channel outputs. 00 7.5 s 01 10.0 s ( same as arinc 429 low speed) 10 10.0 s ( same as arinc 429 low speed) 1 1 1.5 s ( same as arinc 429 high speed) 0 rxsel r/w 0 selects either the hbp (0) or bprz (1) receiver . this bit is logically ord with the rsel input pin. 7 6 5 4 3 2 1 0 msb lsb br0 32wps slew1 slew0 rxsel br1 br2 control register 0: ctrl0 read: spi op-code 0xe4 w rite: spi op-code 0x64 register descriptions x * in the case of f ast instructions, the last four bits of the instruction byte are data t able 2. spi instruction set h o l t i n t e g r a t e d c i r c u i t s 6 hi-3717
hi-3717 h o l t i n t e g r a t e d c i r c u i t s 7 register descriptions (cont.) bit name r/w default description 7 insync r 0 receive channel sync indicator . the bit is set to1 when synchronization is achieved on the receive channel. normal synchronization occurs when four consecutive valid sync marks (octal 1 107, 2670, 5107 and 6670 respectively) are received exactly 1 second apart. the bit is set when the next valid and properly spaced subframe sync mark (octal 1 107) is detected. software synchronization (ctrl1<2> = 1) occurs when two consecutively valid sync marks are received exactly 1 second apart and in the proper order but the first sync mark does not have to be octal 1 107. the bit is set when the next valid and properly spaced subframe sync mark is detected. the bit remains set until synchronization is lost at which time the device automatically attempts to re-synchronize. no data is passed to the receive fifo until synchronization is re-established. existing data in the fifo remains intact and can be read at any time. 6-5 sync0:1 r 0 the two bits are a realtime indicators of when each of the four arinc 717 subframe sync marks are received. they are updated when the sync mark is detected and passed to the receive fifo. the two bits are only valid when insync is 1 00 subframe sync1 mark received (octal 1 107) 01 subframe sync2 mark received (octal 2670) 10 subframe sync3 mark received (octal 5107) 1 1 subframe sync4 mark received (octal 6670) 4 rffull r 0 bit is set when the receive fifo contains 32 words. 3 rfhalf r 0 bit is set when the receive fifo contains exactly 16 words. 2 rfempty r 1 bit is set when the receive fifo is empty . it is reset to0 when the first valid word is passed to the receive fifo. 1 rfovf r 0 fifo overflow bit and rovf pin are set to 1 when devices attempts to load a valid word to a full receive fifo. the receive fifo will ignore additional words if it is full. 0 - r 0 not used, always reads 0 7 6 5 4 3 2 1 0 msb lsb rffull rfhalf test sync0 i n s y n c receive fifo st a tus register: rxfst a t read: spi op-code 0xe6 w rite: read only x x x x rfovf rfempty bit name r/w default description 7 - 4 - r/w 0 not used, always reads a 0 3 srst r/w 0 software reset - setting this bit to 1 empties all the fifo s, clears the sync detection logic and sets the analog line drivers to hi-z state. all other register bits remain unchanged. 2 sftsync r/w 0 software synchronization - setting the bit to 1 will result in the insync output pin going high when the third of three consecutively occurring sync marks is detected. 1 nosync r/w 0 no synchronization - setting this bit to 1 will result in all data captured being loaded into the receive fifo. w arning: in this mode there is no way the hi-3717 can determine frame or sub- frame boundaries. this sync mode overrides all the other sync modes when set to 1. 0 test r/w 0 t est mode - a 1 in this bit position will disable the line receiver and both line drivers and the digital transmitted data will be looped back to the hbp or bprz data sampler selected by rxsel . 7 6 5 4 3 2 1 0 msb lsb srst test control register 1: ctrl1 read: spi op-code 0xe2 w rite: spi op-code 0x62 x x x x nosync sftsync s y n c 1 x x x x t able 4. t able 5.
h o l t i n t e g r a t e d c i r c u i t s 8 hi-3717 the w ord count utility register can be programmed to generate an interrupt on the ma tch pin when the data for the specified word count of the specified subframe is loaded into the receive fifo. the w ord count utility register can used with any of the standard arinc 717 data rate and all of the expanded data rates, except 8192 wps. bit name r/w default description 15 - 3 c12:0 r/w 0 subframe w ord count - the value is compared to the current word count in the receive fifo and sets the ma tch pin to 1 whenever there is a match. the ma tch pin will stay at 1 for one word time. 2 - r/w 0 not used, always reads 0 1 - 0 s1:0 r/w 0 subframe id 00 subframe one 01 subframe t wo 10 subframe three 1 1 subframe four 7 6 5 4 3 2 1 0 lsb c1 c0 so c2 c 4 word count utility register: wrdcnt read: spi op-code 0xf2 w rite: spi op-code 0x72 x x x x s1 ffempty c 3 x x x x register descriptions (cont.) bit name r/w default description 7 tffull r 0 set when the t ransmit fifo contains 32 words 6 tfhalf r 0 set when the t ransmit fifo contains exactly 16 words 5 tfempty r 1 set when the t ransmit fifo is empty . reset to 0 when at least one word is loaded to the t ransmit fifo. 4 - 0 - r 0 not used, always reads 0 7 6 5 4 3 2 1 0 msb lsb f ffull ffhalf test tfempty t f f u l l transmit fifo st a tus register: txfst a t read: spi op-code 0xe8 w rite: read only x x x x ffovfw ffempty t f h a l f x x x x bit name r/w default description 7 - 6 rfifo1:0 r/w 0 these bits program which receive fifo status register bit is represented by the rfifo pin . 00 rfifo pin is set 1 when receive fifo status register bit 2, rfempty , is 1. 01 rfifo pin is set 1 when receive fifo status register bit 3, rfhalf , is 1. 10 rfifo pin is set 1 when receive fifo status register bit 3, rfhalf , is 1. 1 1 rfifo pin is set 1 when receive fifo status register bit 4, rffull, is 1. 5 tfifo r/w 0 the bit programs which t ransmit fifo status register bit is represented by the tfifo pin. 0 tfifo pin is set 1 when t ransmit fifo status register bit 7, ttfull, is 1. 1 tfifo pin is set 1 when t ransmit fifo status register bit 6, tfhalf , is 1. 4 - 0 - r 0 not used, always reads 0 7 6 5 4 3 2 1 0 msb lsb f ffull ffhalf test tfifo r f i f o 1 fifo st a tus pin assignment register: fspin read: spi op-code 0xea w rite: spi op-code 0x6a x x x x ffovfw ffempty r f i f o 0 x x x x 15 14 13 12 1 1 10 9 8 msb c9 c8 c5 c10 c 1 2 x x x x c6 c7 c 1 1 x x x x t able 6. t able 7. t able 8.
time 1 s e c o n d 1 s e c o n d 1 s e c o n d msb lsb 0 1 1 8 2 1 1st subframe sync code (1 107) lsb msb 9 10 1 0 0 0 3 example 1. w rite t ransmit fifo subframe sync or data w ord . (op-code 0x74) 6 5 4 7 lsb msb 0 3 9 10 nth data w ord 2 1 1 1 8 5 6 7 4 subframe sync or data w ord bits spi op-code example 3. fast w rite t ransmit fifo subframe sync or data w ord . (op-code 0x2-) msb lsb 9 8 5 x 1 6 7 10 1 1 12 0 0 3 2 1 4 w ord count bits 0 spi op-code msb lsb 1 1 1 0 0 1 0 example 4. w rite w ord count utility register , wrdcnt . (op-code 0x72) msb lsb 1 1 8 2 1 9 10 0 3 6 5 4 7 sync bits always 0 1 spi op-code msb lsb 1 1 1 1 1 1 0 example 5. read receive fifo data w ord with w ord count . (op-code 0xfe) msb lsb 9 8 5 0 1 6 7 10 1 1 12 0 0 3 2 1 4 subframe sync or data w ord bits w ord count bits msb lsb 0 1 1 8 2 1 9 10 0 0 0 0 3 6 5 4 7 subframe sync or data w ord bits always 0 1 spi op-code msb lsb 1 1 0 0 1 1 0 example 2. read receive fifo subframe sync or data w ord . (op-code 0xf6) always 0 0 spi op-code dont care msb lsb 1 1 1 0 1 0 0 msb lsb x 1 1 8 2 1 subframe sync or data w ord bits 9 10 x x x 0 3 6 5 4 7 lsb msb 2nd data w ord 4 s e c o n d s 1 s e c o n d sync bits 0 1 3 0 4 2 0 0 1 0 1 1 0 0 0 0 1 the first 12- bit word of a subframe that appears on the arinc 717 bus is the synchronization code with the least significant bit (lsb) first. this is immediately followed by up to 8191 12-bit data words, all within1 second from the start of the synchronization code. the next three subframes immediately follow the first subframe with their synchronization code as the first 12-bit word of the subframe followed by the same number of data words as the first subframe. arinc 717 data is transmitted between the hi-3717 and host microcontroller using the four-wire serial peripheral interface (spi). a read or write operation consists of a single-byte op-code followed by 8-bit data words. figure 5 shows examples of how the spi data bytes are mapped to the arinc 717 message. f r a m e msb s u b f r a m e 3 lsb msb lsb msb lsb s u b f r a m e 4 s u b f r a m e 1 1 s e c o n d msb lsb s u b f r a m e 2 arinc717 subframe format arinc717 message as received / transmitted on the arinc 717 serial bus arinc 717 messages consist of 12-bit words sent in a 4 second frame divided into four 1 second subframes. each subframe consists of 64 (basic rate), 128, 256, 512, 1024, 2048, 4096 or 8192 12 bit words, depending on the data rate of the target system. the first word of each subframe contains a unique barker code synchronization pattern that identifies the subframe. the octal synchronization code for subframes 1 through 4 are 1 107, 2507, 5107 and 6670 respectively . 1 1 10 9 8 7 6 5 1 0 0 0 arinc 717 message and bit ordering arinc 717 message as transferred on the spi bus hi-3717 h o l t i n t e g r a t e d c i r c u i t s 9 figure 5. arinc 717 & spi bit ordering
over view arinc 717 is a continuous transmission of 12-bit words in 4 second frames divided into four 1 second subframes. the programmed data rate (32 to 8192 wps) determines the number of words per subframe. the first word of each subframe is reserved for a unique sync mark. figure 5 illustrates the relationship between arinc 717 frames, subframes and words. the hi-3717 is comprised of independent arinc 717 receive and t r a n s m i t s e c t i o n s e a s i l y a c c e s s i b l e v i a a f o u r w i r e s p i communications bus. it supports the arinc 717 harvard bi-phase (hbp) protocol as well as the bi-polar return to zero (bprz) auxiliary protocol. the receiver accepts data from either a harvard bi-phase (hbp) or a bi-polar return to zero (bprz) bus, recovers the clock, decodes the data, synchronizes the arinc 717 data frames using the unique subframe sync marks and stores the recovered data in a 32 word x 12 bit receive fifo. the arinc 717 t ransmitter accesses data from a 32 word x 12 bit t ransmit fifo, encodes it into both hbp and bprz data streams at the selected data rate, and converts the digital data stream to arinc 717 bus compatible outputs. there are separate outputs for the hbp and bprz arinc 717 buses. the receive and transmit sections operate at the same data rate and they are configured and monitored via the spi interface. refer to figure 1 for the block diagram of the hi-3717 initializa tion and reset the hi-3717 generates a full reset upon application power . the power-on-reset (por) sets all registers to their default values, places the receive and t ransmit fifos to their empty state, and clears the sync detection logic. it also sets both the hbp and bprz outputs to the high impedance state and the input sampling and decoders are disabled. see register descriptions for complete definition of the default values. the part can also be initialized to the full reset state by applying a 100ns active low pulse to the external mr pin. a software reset is also possible via the spi communications interface by writing a 1 to the ctrl1<3>. this bit places both the receive and t ransmit fifo s in the empty state, clears the sync detection logic, and sets both the hbp and bprz line drivers to a high impedance state. all other registers remain unchanged. the device is held in the reset state until a 0 is written to ctrl1<3>. configura tion the hi-3717 is configured via the spi communications bus by writing to control register 0, ctrl0, and control register 1, ctrl1. they are reset to 0x00 following a power on reset (por) or a master reset (mr) but remain unchanged on a software reset, ctrl1<3>, srst . the function of each register bit is shown in the register descriptions. in order to avoid inadvertent transceiver operation, control register 0, ctrl0, should be programmed last. w riting ctrl0 sets the desired data rate which, after one bit period, the internal clocks are enabled. this in turn makes the transmitter or receiver operational. changing the data rate on the fly may result in unpredictable operation during the transition to the new programmed state. a full reset, por or mr, should be issued before reprogramming the data rate. data rate for correct arinc 717 date rate reception, transmission and bit timing, the hi-3717 requires a 24 mhz reference clock source applied to the aclk input. this clock is divided down to achieve the data rate programmed with cntl0<6:4>. the input receive data is 8x oversampled relative to the programmed data rate. arinc 717 requires a basic data rate of 64 wps with support for 128, 256 and 512 wps. the hi-3717 of fers an expanded range of 32 to 8192 wps for testing purposes and future expansion. ctrl0<3>, 32wps, overrides the state of ctrl0<6:4> and sets the data rate to 32 wps. the required 0.1% timing tolerance is maintained over all data rates. line driver output slew rates the slew rate of the hbp and bprz outputs is controllable with cntr0<2:1>. a 7.5s slew rate conforms to all the required arinc 717 data rates. in addition, a 1.5s is provided for the higher data rates and a 10s for the 32 wps data rate. receiver format the arinc 717 format of the receiver is selectable as hbp or bprz by the state in cntl0<0>, rxsel, ord with the state of the external rsel input pin. a 0 on rsel and cntl0<0> selects hbp and a 1 on either rsel or cntl0<0> selects bprz. refer to t able 3 for the detail description of each bit in control register 0. input synchronization mode the hi-3717 has three dif ferent synchronization modes, depending on how it is being used. 1. flight recorder mode this is the normal synchronization mode. in this mode the hi-3717 searches for the four subframe sync marks: sync1 = octal 1 107 sync2 = octal 2670sync3 = octal 5107 sync4 = octal 6670 in the correct sequential order starting from sync1 and the exact bit time determined by the programmed word rate. when synchronization is achieved the insync pin as well as the insync bit of the receive fifo status register , rxfst a t<7> are set to 1 on the next valid sync1 mark. the valid sync1 mark and following data words are stored in the receive fifo. sync time varies from 4 seconds to a worst case of 8 seconds for a valid data stream. functional description h o l t i n t e g r a t e d c i r c u i t s 1 0 hi-3717
0 msb 1 0 0 1 1 1 0 1 0 1 +5v harvard bi-phase -5v +10v bi-polar return to zero -10v figure 6. arinc 717 hbp & bprz differential input signal format functional description (cont.) data 1 lsb the first word stored in the receive fifo is available when rxfst a t<2>, rfempty , is reset to 0, which is 12-bit periods (one word time) after insync is set to 1. the hi-3717 remains in sync as long as the proper sync sequence is maintained. insync is reset to 0 when the next expected subframe sync mark is not present. the hi-3717 will initiate a new synchronization process at the next valid sync1 mark. once the part falls out of sync, the whole previous subframe should be discarded. 2. t est mode in this mode the hi-3717 searches for any two subframe sync marks in the correct sequential order and the exact starting time for the sync mark. insync is set to 1 when the third valid sync mark is detected. the part must continue to detect each sync mark in the correct order and with the correct starting time to stay in sync. this method reduces the time required to obtain sync to about 2 seconds typical and a worst case of 3 seconds. 3. no sync detect mode in this mode, the insync is set to 1 and all data is stored in the receive fifo. without sync detection, the receive fifo just records the sequential bits, not words, from the bus. it is up to the user to detect the sync marks and determine the word boundaries in this mode. in both the flight recorder mode and the t est mode, the hi-3717 uses a proprietary sync tracking and detection method which allows multiple random false sync marks in the user data without increasing the sync time. digital loopback normal hi-3717 operation is with ctrl1<0> set to 0. setting it to 1 places the part in digital loopback mode. in this mode the analog line receivers are disconnected from the data samplers and both output line drivers are placed in a high impedance state. the output encoders are connected to input sampler / decoder . the part may be verified by selecting the desired receive decode format with rsel pin or ctrl1<0>, writing the transmit fifo and reading the receive fifo. all status pins and registers reflect the status of the loopback operation. fifo status pin assignment register , fspin this register assigns the function of the external rfifo and tfifo pins. the rfifo pin reflects the state of one of the three receive fifo status flags (rffull, rfhalf and rfempty) in the receive fifo status register , rxfst a t . the tfifo pin reflects the state of one of two t ransmit fifo status flags (tfull or tfhalf) in the tfxst a t register . refer to the fspin register description in t able 7 for register assignment details. w ord count utility register , wrdcnt the ma tch pin goes high when the hi-3717 is in the insync condition and the word count and subframe count matches the value programmed in the w ord count utility register . note: the insync pin is set to 1 when the second consecutive sync1 mark of the proper sync sequence is received. the w ord count utility register and match pin function can be used for the standard arinc 717 data rates and all of the expanded data rates, except 8192 wps. arinc 717 receiver the input data stream for arinc 717 can be one of two formats. the main arinc 717 bus to a digital flight data recorder (dfdr) uses harvard bi-phase (hbp) encoding and the auxiliary output bus to an aircraft integrated data system (aids) uses bi-polar return to zero (bprz) encoding as shown in figure 6. the hi-3717 has an independent arinc 717 receive channel with a selectable on-chip hbp analog line receiver for connection to the main incoming arinc 717 data bus or a bprz analog line receiver for connection to an auxiliary data bus. the arinc 717 specification requires the following detection levels for the hbp inputs: st a te differential vol t age hi +2 v olts to +8 v olts null na lo -2 v olts to -8 v olts hi-3717 h o l t i n t e g r a t e d c i r c u i t s 1 1
differential amplifiers comp ara t ors figure 7. arinc 717 receiver inputs rina-40 rina rinb rinb-40 vdd gnd vdd gnd one null zero the auxiliary bprz input detection levels are the same as standard arinc 429 levels: st a te differential vol t age one +6.5 v olts to +13 v olts null +2.5 v olts to -2.5 v olts zero -6.5 v olts to -13 v olts the hi-3717 guarantees recognition of these levels with a common mode voltage with respect to gnd less than 25v for the worst case conditions (3.15v supply , 8v hbp signal level and 13v bprz signal level). design tolerances guarantee detection of the above levels, so the actual acceptance ranges are slightly larger . if the signal (including nulls) is outside the dif ferential voltage ranges, the hi-3717 receiver rejects the data. bit t iming & input sampling the bit timing for both the receive and transmit functions is the data rate programmed in ctrl0<6:3>. the hi-3717 allows the following word / bit rates: the input data from the selected analog line receiver is oversampled at 8x relative to the word rate programmed in ctrl0<6:3>. this is 4x oversample of the transition rate since the code rate for both methods is double the data rate. the sampler uses three separate shift registers, one each for ones, zero and null detection. when the input signal is within the dif ferential voltage range of one of the valid states (one, zero or null) of the selected data format, the sampler clocks 1 into that register and a 0 into the other two. when the signal is outside the dif ferential voltage ranges defined for all the shift registers, a 0 is clocked into all three registers. only one shift register can clock 1 for a given sample. the null shift register is only used for the bpnz format. 32 words/sec. = 384 bits/sec 64 words /sec. = 768 bits/sec. 128 words/sec. = 1536 bits/sec. 256 words/sec. = 3072 bits/sec. 512 words /sec. = 6144 bits/sec. 1024 words/sec. = 12288 bits/sec. 2048 words/sec. = 24576 bits/sec. 4096 words/sec. = 49152 bits/sec. 8192 words/sec. = 98304 bits/sec. the 32 wps data rate is typically used for testing purposes. for havard bi-phase, hbp , coding, the sampler validates a hi (one) or lo (zero) if the signal is in that state for at least two samples. there is no null state for the hbp format. the bi-polar return to zero, bprz, coding sampler validates that at least two consecutive ones or two consecutive zeroes are followed by at least two consecutive null states. decoders the decoder recovers the clock and resynchronizes each valid one or zero to the transition bit period. the harvard bi-phase, hbp , decoder confirms the sampler only provided a valid one or zero, not both, then detects the presence of absence of an edge in the data bit period. the output of the decoder is a 1 if there was a transition, otherwise a 0. the bi-polar return to zero, bprz, decoder confirms the sampler only provided a valid one or zero, followed by a valid null. the decoder output is a 1 for a valid one and 0 for a valid zero. once the data is captured, it is re-sampled to the recovered transition rate clock (sample clock sent to the sync detector) and re- sampled to recover the data bit rate clock. the decoders will operate correctly when the input data bit period is not more than 2 sample clocks (25%) larger or 1 sample clock (12.5%) smaller than the nominal value. the slower input frequency causes a mismatch between the sampled data and the recovered clock. the faster input frequency causes issues with internal edge detection logic. any incorrectly decoded data will cause the next sync mark to be missed and the insync bit to go to 0. sync detect the hi-3717 employs a proprietary , four level sync algorithm that samples each bit and compares each combination of 12-bits against the four valid arinc 717 subframe sync marks. in the flight mode, once a valid sync1 mark is discovered, it continues to look for each of the next three subframe sync marks in the proper order and timing. if any one is not found, the search starts over looking for sync1 again. once all four sync marks are detected in the proper order and location in a frame, the insync pin is set to 1 at the next sync1 subframe sync mark if it is the correct value and it occurs at the proper relationship to the previous valid sync mark. this is the default synchronization mode for the hi-3717. in the software synchronization mode, ctrl1<2> = 1, once two consecutive valid subframe sync marks are detected, the insync bit is set to 1 at the next consecutive valid subframe sync mark if it occurs at the proper relationship to the previous valid sync marks. the first valid subframe sync mark does not have to be sync1 in this mode but each successive subframe sync marks must be the next in the sequence and properly spaced from the preceding valid subframe sync mark. insync is set to 0 when the next expected subframe sync mark is missed in the flight mode and software synchronization modes. the hi-3717 sync detection logic is reset and the part initiates the full synchronization process again. the data from the subframe preceding the first incorrect subframe sync mark should be discarded. no data is passed to the receive fifo until synchroni- zation is reestablished. cntl0<0> rsel functional description (cont.) h o l t i n t e g r a t e d c i r c u i t s 1 2 hi-3717
figure 8. arinc 717 receiver block diagram bprz decoder shift register shift register ones rsel shift register rfifo to line drivers hbp / bprz select hbp decoder sync detection word clock da t a clock divider ctrl0<0> zeros 12-bit serial register word count & subframe detection 32 word x 12-bit receive fifo 12-bit serial input register 12-bit serial input register insync rovf sync1 sync0 12-bit comp ara t or aclk null ctrl0<6:4> there are also two bits in the receive fifo status register , rxfst a t<6:5> that provide a realtime indicator when each of the four arinc 717 subframe sync marks are received. the bits are valid only when insync is 1 and are updated when the subframe sync word is loaded into the receive fifo. the final mode is no synchronization, cr tl1<1> = 1. in this mode data is captured and loaded directly to the receive fifo in the order it was received. it is the responsibility of the user to extract the data from the fifo and determine word, frame and subframe boundaries. the insync bit remains 0 while in this mode. receive fifo and retrieving data data is transferred from the receive fifo starting with the valid subframe sync mark when insync was set to 1 and continues with each consecutive 12-bit word until insync is set to 0. each time a valid arinc 717 word is loaded to the receive fifo the rffull, rfhalf and rfempty bits in the receive fifo status register (rxfst a t<4:2>) are updated. each word is retrieved from the receive fifo via the spi interface using spi op-code instruction 0xf6 (word only), 0xfe (word & word count) or 0xc (fast read). the spi read instruction 0xf6 format is an 8-bit op-code followed by two 8-bit data words. the four most significant bits (msb) of the first data word are always 0 followed by the first four msb of the arinc 717 word. the second data word contains the remaining 8-bits of the arinc 717 word. the least significant bit (lsb) of the arinc 717 word is the lsb of the second 8-bit data word. the format for read word and word count instruction 0xfe is the same as the read instruction with the addition of two additional 8-bit data bytes that contain the word count and the corresponding sync subframe information. the third 8-bit spi data byte contains the 8 msb bits of the word count. the fourth data byte is comprised of remaining 5 bits of the word count as well as the two bit code for the subframe number in the same format as described in the rfxst a t register description. refer to example 5 in figure 5 for more details on the format for this instruction. the fast read instruction 0xc uses only one spi data byte for a read operation. this is accomplished by using only first four bits for the spi op-code and placing the first four most significant bits of the arinc 717 word in the four remaining bit locations of what are normally part of an op-code. the remaining 8-bits of the arinc 717 word are in a normal spi data byte. this method use one less spi data byte than a normal read instruction. up to 32 arinc 717 words may be held in the receive fifo. the rffull bit (rxfst a t<4>) is set to 1 when the receive fifo is full. failure to unload the receive fifo when full will result in loss of new data words until there are less than 32 words in the fifo. the rfovf bit (rxfst a t<1>) and external frov pin are set to 1 when an attempt is made to write to a full receive fifo. the receive fifo half-full flag, the rfhalf bit (rxfst a t<3), is set to 1 whenever the receive fifo contains exactly 16 words. the rfhalf bit provides a useful indicator to the host cpu that the fifo is filling up. the receive fifo empty , the rfempty bit (rxfst a t<2>), is set to 1 when the receive fifo is empty . it is reset to 0 when there is at least one word in the receive fifo. when the hi-3717 attempts to load a valid word to a full receive fif0, the rfovf flag, rxfst a t<1>, and the external rfov pin are set to 1. the receive fifo ignores any attempt to load any additional words if it is full. the rfovf flag and rfov pin are reset to 0 when either the insync goes to 0 or the device is reset. the external rfifo pin is programmable in the fifo status pin assignment register (fspin<7:6>) to reflect the value of the rffull, rfhalf or the rfempty status bit. refer to the fspin register description for the bit values that assign the rffull, rfhalf or rfempty status bit to the rfifo pin. the default state is assignment of the rfempty bit to the rfifo pin. w ord count utility register , wrdcnt , is used to cause the external ma tch pin to be set to1 when a specific word count is reached in a specific subframe. wrdcnt<15:3> specifies the location in the subframe and wrdcnt<1:0> specifies the subframe that is monitored. ma tch is 1 until the next word is loaded into the receive fifo. the match word and subframe bit assignments of the w ord count utility register , wrdcnt , are found in t able 8. functional description (cont.) h o l t i n t e g r a t e d c i r c u i t s 1 3 hi-3717
transmitter fifo operation the hi-3717 t ransmit fifo is loaded with arinc 717 words awaiting transmission. spi words are written to the next t ransmit fifo location with op-code 0x74 or 0x2 (fast w rite). if t ransmit fifo status register empty flag, the tfempty (txfst a t<5>) bit, is 1 (fifo empty), then up to 32 arinc 717 12-bit words can be safely loaded via the spi interface. if the tfempty bit is 0 then less than 32 positions are available. if all 32 positions are filled, then the full flag, the tffull (txfst a t<7>) bit, is 1. all attempts to load the t ransmit fifo are ignored until the tffull bit is 0 which indicates that at least one word can be loaded. the t ransmit fifo half-full flag, the tfhalf (txfst a t<6>) bit in the t ransmit fifo status register , is equal to 0 when there are less than or more than 16 arinc 717 words in the t ransmit fifo and equal to 1 when there are exactly 16 words in the fifo. the host cpu can safely load 16 arinc 717 words into the t ransmit fifo only when tfhalf is 1. the state of the tffull or tfhalf is available on the external tfifo pin, depending on the value in fspin<5> of the fifo status pin assignment register (see t able 7). the state of tfempty flag is always on the external tempty pin. it is the user s responsibility to load the correct subframe sync mark in the first word of each subframe and ensure the t ransmit fifo is not left empty for more than one word time for continuous transmis- sions. the spi format for writing an arinc 717 word and fast w ord to the hi-3717 t ransmit fifo is the same as the read format, except the most significant bit of the op-code instruction is 0 rather than a 1. data t ransmission the arinc 717 transmission begins when the first word is loaded into the t ransmit fifo. each word is serially fed to both the hbp and bprz encoders at the data rate programmed in control register 0, cntl0<6:4>. the output of each encoder drives its own arinc 717 analog line driver . the slew rate of both the hbp and the bprz auxiliary outputs is controllable with cntl0<2:1>. refer to the ctrl0 register description for the individual bit values required for setting the desired data and output slew rate. system operation the receiver and transmitter always operate at the same data rate. otherwise, they operate completely independent of each other . the only restrictions are: 1. the receive fifo ignores any attempt to load any additional words if it is full and at least one location is not retrieved before the next valid arinc 717 is received. 2. the t ransmit fifo can store a maximum of 32 words and ignores any attempt to store additional words when it is full. dc/dc converter the hi-3717 requires only a single +3.3v power supply . an integrated inverting / non-inverting voltage doubler generates the rail voltages (5.7v) which then power the line drivers to produce the required +5v arinc 717 hbp and 5v arinc 717 bprz signal levels. the internal dual-polarity charge pump requires four external capacitors, two for each polarity generated by the charge pump. functional description (cont.) h o l t i n t e g r a t e d c i r c u i t s 1 4 hi-3717 bprz encoder figure 9. arinc 717 t ransmitter block diagram da t a clock aclk hbp encoder slew ra te & loopback test control hbp line driver word clock & bit clock st ar t sequence word counter & fifo control increment word count da t a clock divider fifo loading sequencer txba txouthb, outhb 32 word x 12 bit fifo 12 bit p arallel load shift register bit clock word clock address ctrl0<6:4> tfifo noconv tempty spi interf ace sck cs si so spi commands spi commands bprz line driver txoutba, outba txoutbb, outbb load txoutha, outha txbb txha txhb
pins c1+ and c1- connect the external fly capacitor , cfl y , to the positive portion of the charge pump, resulting in 5.7v at the v+ pin that is generated by an on-board bandgap reference voltage. an output hold capacitor , cout , is placed between v+ and gnd. cout should be ten times the size of cfl y . the inverting negative portion of the converter works in a similar fashion, with cfl y and cout placed between c2+ / c2- and v - / gnd respectively . note that low esr capacitors should be used. recommended values are given in the block diagram on page 2. line driver operation the line drivers in the hi-3717 directly drive the arinc 717 buses. the two arinc 717 hbp outputs (txoutha and txouthb) provide a dif ferential voltage of 5v in accordance w i t h t h e h a r v a r d b i - p h a s e f o r m a t . c o n t r o l r e g i s t e r 0 ( c t r l 0 < 6 : 4 ) c o n t r o l s t h e t r a n s m i t t e r d a t a r a t e a n d ctrl0<<2:1> controls the output slew rate. the two auxillary arinc 717 bprz outputs (txoutba and txoutbb) provide a dif ferential voltage to produce a +10v one, a -10v zero, and a 0 v olt null. the transmitter data rate is the same as the hbp output which is also controlled by the same bits in control register 0 (ctrl0<6:4). the slew rate of the dif ferential output signal is also controlled by control register 0 (ctrl0<2:1>. no additional hardware is required to control the slope. slope rate is set by an on-chip resistors and capacitors. line driver output pins the harvard bi-phase (hbp) txoutha and txouthb pins as well as the bi-polar return to zero (bprz) txoutba and txoutbb pins have 37.5 ohms in series with each line driver output, and may be directly connected to an arinc 717 bus. the outha, outhb, outba and outbb pins have 5 ohms of internal series resistance and require an external 32.5 ohm resistor in series with each pin. outha, outhb, outba and outbb pins are for applications where external series resis- tance is applied, typically for lightning protection devices. either the txoutha & txouthb outputs or the outha & outhb outputs are used in an application but not both sets at the same time. likewise, only one set of the auxiliary bprz output pins (txoutba & txoutbb or outba & outbb) are used. using both set of pins on either output will produce unpredictable results. the line driver outputs txoutha, txouthb, outha, outhb, txoutba, txoutbb, outba & outbb are in a high imped- ance state after any reset and when in the digital loopback test mode (ctrl1<0> = 1) allowing multiple line drivers to be connected to a single arinc 717 bus. note that both analog line receivers are also disconnected from the hbp and bprz input data samplers during reset and when in the digital loopback mode. the hi-3717 also has digital outputs from both the hbp (txha & txhb) and the bprz (txba & txbb) encoders allowing the use of external arinc 717 line drivers. all four of these output pins are active all the time and reflect the digital data sent to the data sampler in the digital loopback mode. line receiver input pins the hi-3717 has two sets of line receiver input pins that are shared with the hbp and bprz line receivers, rina/b and rina/b-40. only one pair may be used to connect to the arinc 717 bus. the unused pair must be left floating. the rina/b pins may be connected directly to the arinc 717 bus. the rina/b-40 pins require an external 40k ohm resistor in series with each arinc 717 input. the resistors do not af fect the arinc 717 receiver level detection thresholds . when using the rina/b-40 pins, each side of the arinc 717 bus must be connected through a 40k ohm series resistor in order for the chip to detect the correct arinc 717 levels. the typical arinc 717 dif ferential signal is translated and input to a window comparator and latch. the comparator levels are set so that with the external 40k ohm resistors, they are just below the standard minimum data threshold and in the case of the auxiliary bprz line receiver , just above the standard 2.5 volt bprz (arinc 429) null threshold. by keeping excessive voltage outside the device, the rina/b-40 input option is helpful in applications where lightning protection is required. please refer to the holt an-300 application note for additional in- formation and recommendations on lightning protection of holt line drivers and line receivers. master reset application of a master reset with a 100ns active low pulse to the external mr pin sets all registers to their default values, places the receive and t ransmit fifos to their empty state, and clears the sync detection logic. it also sets both the hbp and bprz out- puts to the high impedance state and disables input sampling of both analog line receivers.. software reset a software reset is also possible via the spi communications in- terface by writing a 1 to the ctrl1<3>. this bit places both the receive and t ransmit fifo s in the empty state, clears the sync detection logic, sets both the hbp and bprz line drivers to a high impedance state and disables the input sampling of both analog line receivers. unlike por and mr, all other registers remain unchanged. the device is held in the reset state until a 0 is writ- ten to ctrl1<3>. no dc/dc converter option the noconv pin is set to 1 to disable the internal dc/dc con- verter and supply +5v & -5v to the v+ & v - pins respectively from an external power source. the fly capacitor pins can be left floating. no internal line drive option the hi-3717 can be used without the internal line drivers if only the arinc 717 receive function is required or if the user wants to use his own external arinc 717 line drivers connected to the txah, txbh, txab & txbb digital transmitter outputs. for this option, noconv pin is set to 1 to disable the internal line driv- ers, v+ is connected to vdd & v - is left unconnected. functional description (cont.) h o l t i n t e g r a t e d c i r c u i t s 1 5 hi-3717
cs sck so chz t hi impedance sckh t t dv lsb cph t t sckl msb hi impedance cs sck si chh t ceh t msb ces t ds t t dh lsb cph t sckr t sckf t ces t cyc t cyc t timing diagrams hbp da t a last transmit fifo word tempty 2nd to last word bit 5 bit 1 1 bit 10 bit 9 bit 8 bit 7 bit 6 bit 4 bit 3 bit 2 bit 1 bit 0 bit 1 1 bit 10 bprz da t a t tempty hbp da t a rovf bprz da t a t rovf insync 12 data bits rfifo (rfempty) 12 data bits t rempty rfifo ( rffull ) figure 13. t ransmit fifo empty flag t iming figure 10. spi serial input t iming figure 1 1. spi serial output t iming figure 12. receive fifo flag t iming h o l t i n t e g r a t e d c i r c u i t s 1 6 hi-3717
figure 14. harvard bi-phase (hbp) output w aveforms hbp bit data bit 1 hbp bit data bit 1 1 hbp bit data bit 0 +5v -5v -5v one level zero level 90% 90% 10% 10% t fx t rx 0v 0v +5v +5v +5v +5v 0v +5v 0v +5v 0v 0v txoutha & outha txouthb & outhb v diff (txoutha - txouthb & outha - outhb) +3.3v +5v t bf t br 0v 0v +3.3v +3.3v 0v +3.3v 0v txba txbb 0v +3.3v +3.3v 0v +3.3v 0v bi-polar return zero (bprz) txhb figure 16. harvard bi-phase (hbp) & bi-polar return to zero (bprz) logic output w aveforms data bit 1 data bit 1 1 data bit 0 figure 15. bi-polar return to zero (bprz) output w aveforms bprz bit data bit 1 bprz bit data bit 1 1 bprz bit data bit 0 +5v +5v +5v +10v +10v -10v -5v -5v -5v one level zero level null level 90% 90% 10% 10% t fx t rx t fx t rx one level null level 90% 90% 10% 10% t hf txoutba & outba txoutbb & outbb v diff (txoutba - txoutbb & outba - outbb) 0v 0v +3.3v 0v txha har v ard bi-phase (hbp) t hr 90% 90% 10% 10% zero level timing diagrams (cont.) h o l t i n t e g r a t e d c i r c u i t s 1 7 hi-3717
v dd = 3.3v , t a = operating t emperature range (unless otherwise specified). dc electrical characteristics limits p arameter symbol conditions unit min typ max har v ard bi-phase (hbp) inputs - pins rina, rinb, rina-40 (with external 40kohms), rinb-40 (with external 40kohms) hbp dif ferential input v oltage: (rina to rinb) hi v ihh common mode voltages less than 2.0 5.0 8.0 v lo v ilh 25v with respect to gnd -8.0 -5.0 -2.0. v hbp input v oltage (ref. to dfdau signal ground) hi v ihha 3.5 5.0 6.5 v rina lo v ilha -1.5 0 +1.5 v hi v ihhb -1.5 0 +1.5 v rinb lo v ilhb 3.5 5.0 6.5 v bi-polar return t o zero (bprz) inputs - pins rina, rinb, rina-40 (with external 40kohms), rinb-40 (with external 40kohms) bprz dif ferential input v oltage: (rina to rinb) one v ihb common mode voltages less than 6.5 10.0 13.0 v zero v ilb 25v with respect to gnd -13.0 -10.0 -6.5 v null v inul -2.5 0 +2.5 v bprz input v oltage (ref. to dfdau signal ground) one v ihba 3.25 5.0 6.5 v rina zero v ilba -6.5 -5.0 -3.25 v one v ihbb -6.5 -5.0 -3.25 v rinb zero v ilbb 3.25 5.0 6.5 v har v ard bi-phase (hbp) & bi-polar return t o zero (bprz) inputs input resistance: dif ferential r i - 140 - k t o gnd r g - 140 - k t o v dd r h - 100 - k input current: input sink i ih 200 a input source i il -450 a input capacitance: dif ferential c i (rina to rinb) 20 pf (guaranteed but not tested) t o gnd c g 20 pf t o v dd c h 20 pf logic inputs input v oltage: input v oltage hi v ih 80% vdd v input v oltage lo v il 20% vdd v input current: input sink i ih 1.5 a input source i il -1.5 a pull-down current (mr, si, sck, aclk pins) i pd 60 a pull-up current (cs pin) i pu -60 a h o l t i n t e g r a t e d c i r c u i t s 1 8 hi-3717 supply v oltages v dd ......................................... -0.3v to +5.0v v+ ......................................................... +7.0v v - ......................................................... -7.0v v oltage at pins rinxx-xx .................................. -120v to +120v v oltage at pins txaout , txbout , amp a, ampb ......... v - to v+ v oltage at any other pin ............................... -0.3v to v dd +0.3v solder temperature (leads) .................... 280c for 10 seconds (package) .......................................... 220c power dissipation at 25c plastic quad flat pack ............... 1.5 w , derate 10mw/c dc current drain per digital input pin ........................... 10ma storage t emperature range ........................ -65c to +150c operating t emperature range (industrial): ..... -40c to +85c (hi-t emp): ..... -55c to +125c note: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only . functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may af fect device reliability . absolute maximum ra tings
har v ard bi-phase (hbp) outputs - pins txoutha, txouthb, (or outha, outhb with external 32.5 ohms) hbp output voltage (dif ferential) hi v ohh 600 ohm load 4.0 5.0 6.0 v (txoutha to txouthb or outha to outhb) lo v olh -6.0 -5.0 -4.0 v hbp output voltage (ref to gnd) hi v ohha 600 ohm load 4.5 5.0 5.5 v txoutha or outha lo v olha -0.5 0 +0.5 v hi v ohhb -0.5 0 +0.5 v txouthb or outhb lo v olhb 4.5 5.0 5.5 v bi-polar return t o zero (bprz) outputs - pins txoutba, txoutbb, (or outba, outbb with external 32.5 ohms) bprz output voltage (dif ferential) one v ohb no load 9.0 10.0 1 1.0 v (txoutba to txoutbb or outba to outbb) zero v olb -1 1.0 -10.0 -9.0 v null v onul -0.5 0 +0.5 v bprz output voltage (ref to gnd) one v ohba no load 4.5 5.0 5.5 v txoutba or outba zero v olba -5.5 -5.0 -4.5 v one v ohbb -5.5 -5.0 -4.5 v txoutbb or outbb zero v olbb 4.5 5.0 5.5 v har v ard bi-phase (hbp) and bi-polar return t o zero (bprz) outputs output current i out momentary short-circuit current 80 ma logic outputs (including txha, txhb, txba & txbb) output v oltage: logic "1" output v oltage v oh i oh = -100a 90%vdd v logic "0" output v oltage v ol i ol = 1.0ma 10% vdd v output current: output sink i ol v out = 0.4v 1.6 ma output source i oh v out = v dd - 0.4v -1.0 ma output capacitance: c o 15 pf opera ting vol t age range v dd 3.15 3.45 v opera ting suppl y current t ransmitting data at 8192 words/sec. i dd outputs unloaded 35 ma t ransmitting data in 8192 words/sec. i ddl 600 ohm dif ferential output load hbp 120 ma 400 ohm dif ferential output load bprz v dd = 3.3v , t a = operating t emperature range (unless otherwise specified). dc electrical characteristics (cont.) limits p arameter symbol conditions unit min typ max h o l t i n t e g r a t e d c i r c u i t s 1 9 hi-3717
spi interf ace timing sck clock period cs active after last sck rising edge t chh 5 ns cs setup time to first sck rising edge t ces 5 ns cs hold time after last sck falling edge t ceh 5 ns cs inactive between spi instructions t cph 55 ns spi si data set-up time to sck rising edge t ds 10 ns spi si data hold time after sck rising edge t dh 10 ns sck rise time t sckr 10 ns sck fall ime t sckf 10 ns sck pulse width high t sckh 20 ns sck pulse width low t sckl 25 ns so valid after sck falling edge t dv 35 ns so high-impedance after sck falling edge t chz 30 ns mr pulse width t mr 40 ns receiver timing delay - insync high to rempty low (plus 12 data bits) t rempty 100 ns delay - rffull high to rovf high (plus 12 data bits) t rovf 100 ns transmitter timing tfempy flag high to beginningt of first data bit of last word in t ransmit fifo 32 words / sec. t tempty (32 wps) 2604 s 64 words / sec. t tempty (64 wps) 1302 s 128 words / sec. t tempty (128 wps) 651 s 256 words / sec. t tempty (256 wps) 326 s 512 words / sec. t tempty (512 wps) 163 s 1024 words / sec. t tempty (1024 wps) 81.4 s 2048 words / sec. t tempty (2048 wps) 41.7 s 4094 words / sec. t tempty (4096 wps) 20.4 s 8192 words / sec. t tempty (8192 wps) 10.2 s line driver transition dif ferential times (both the harvard bi-phase and bi-polar return to zero are set to the same slew rate) cntl0<2:1> = 00 high to low t fx 5.0 7.5 10 s low to high t rx 5.0 7.5 10 s cntl0<2:1> = 01 or 10 high to low t fx 5.0 10 15 s low to high t rx 5.0 10 15 s cntl0<2:1> = 1 1 high to low t fx 1.0 1.5 2.0 s low to high t rx 1.0 1.5 2.0 s t ransmitter digital outputs transition times harvard bi-phase (hbp) high to low t hf 3.0 5.0 ns low to high t hr 3.0 5.0 ns bi-polar return to zero (bprz) high to low t bf 3.0 5.0 ns low to high t br 3.0 5.0 ns t cyc 100 ns ac electrical characteristics vdd = 3.3v , t a = operating t emperature range and aclk=24mhz +0.1% limits p arameter symbol units min typ max h o l t i n t e g r a t e d c i r c u i t s 2 0 hi-3717
ordering informa tion hi - 3717 xx x x p ackage description 44 pin plastic chip-scale, qfn (44pcs) p art number pc 44 pin plastic quad fla t p ack, pqfp (44ptqs) pq lead finish p art number 100% matte t in (pb-free, rohs compliant) f t in / lead (sn / pb) solder blank tempera ture range burn in -40c t o +85c no -55c t o +125c no t p art number t i flow i h o l t i n t e g r a t e d c i r c u i t s 2 1 hi-3717 -55c t o +125c y es m m the hi-3717pcx uses a 44-pin plastic chip-scale package. t o enhance thermal dissipation, the heat sink can be this package has a metal heat sink pad on its bottom soldered to matching circuit board pad. surface. this heat sink is electrically isolated from the die. hea t sink - chip-scale p ackage onl y
revision hist or y p/n rev date description of change ds3717 new 08/1 1/1 1 initial release ds3717 a 08/23/1 1 corrected typographical errors. deleted qfn power dissipation reference. ds3717 b 1 1/4/1 1 updated spi to 10mhz, added i limits, corrected example typographical error . dd h o l t i n t e g r a t e d c i r c u i t s 2 2 hi-3717
hi-3717 p ackage dimensions 44-pin plastic chip-scale p ackage (qfn) package t ype: 44pcs bsc = basic spacing between centers is theoretical true position dimension and has no tolerance. (jedec standard 95) .203 .006 (5.15 .15) .016 .002 (0.40 .05) .010 (0.25) .020 (0.50) .008 (0.2) .039 (1.00) .276 (7.00) bsc .203 .006 (5.15 .15) typ typ bottom v iew t op v iew bsc .276 (7.00) bsc max inches (millimeters) package t ype: 0 < < 7 detail a see detail a sq. 44ptqs 44-pin plastic quad fla t p ack (pqfp) .006 (.15) .547 .010 (13.90 .25) .394 .004 (10.0 .10) sq. max. .014 ..002 (.35 .05) .035 .006 (.88 .15) .005 (.13) r min. .012 (.30) r max. .055 .002 (1.4 .05) .063 (1.6) max. .0315 (.80) inches (millimeters) bsc bsc = basic spacing between centers is theoretical true position dimension and has no tolerance. (jedec standard 95) h o l t i n t e g r a t e d c i r c u i t s 2 3

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